Effects of Technology Scaling on Area-Delay Characteristics of RTL Designs: A Case Study
نویسندگان
چکیده
The paper investigates the effects of technology scaling on area/delay characteristics of registertransfer level (RTL) designs. Based on experimental modeling of RTL components and interconnect, whose feature sizes have been scaled down from 1.5 m to 0.25 m, we evaluate the critical path delay and area of several data-paths and report on efficiency of layout and RTL optimization techniques at the 0.25 m technological level.
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